SAN JOSE, California - May 14, 2001 - Forte Design Systems, Inc., today introduced its GigaScale verification methodology and release of version 5.5 of its QuickBench(R) Verification Suite(TM). Both were developed to conquer the challenges inherent in the verification and design of today's large systems and integrated circuits (ICs) and are scaleable as design sizes reach one billion or more gates. Verification and modeling are major challenges in developing systems of this size. Currently, it is not possible to completely model and verify these huge designs at the register-transfer-level (RTL) by using Verilog or VHDL. With Forte's new GigaScale verification methodology and QuickBench 5.5 testbench automation software, designers can model complex systems at ultra fast simulation speeds and begin verifying their designs early in the process to meet increasingly aggressive time to market schedules.

The Forte GigaScale Hub
New in QuickBench 5.5 is Forte's open GigaScale Hub™ technology, the first product resulting from the recently announced CynApps-Chronology intent to merge. With the Hub, users have the freedom to plug in their choice of multiple languages for design and verification. This enables verification teams to write tests and functions in C /Cynlib for high-performance, and call them from Forte's powerful verification language, RAVE. RAVE and C /Cynlib are the first of a series of design and verification plug-ins to the Hub being developed by Forte. With its new Hub technology for verification module plug-ins, QuickBench extends its lead as the easiest-to-use testbench automation tool.

"Because of its new Hub technology, the QuickBench dataflow environment has given us a significant productivity boost with a small learning curve," said Mark Keefer, ASIC manager, White Rock Networks. "We actually began system verification before the RTL was started. In essence, we were able to use Forte's RAVETM language for detailed verification and employ high-performance C for our high-volume data processing. QuickBench 5.5 has given us a solid jump-start in the verification process."

The GigaScale methodology, used with QuickBench, makes it possible to integrate efficiently with traditional design flows and bridges the gaps between design and verification and algorithm and RTL. With Forte's new solution, designers can produce executable specifications that are usable for design and verification throughout the entire development process. High-speed systems and architecture models can be created using Forte's Cynlib/C product, verified with QuickBench using C or RAVE, and then implemented using HDLs such as VHDL and Verilog.

According to Jacob Jacobsson, president and CEO of Forte Design Systems, "The GigaScale verification methodology addresses the next step in large scale design and verification. With this methodology and the QuickBench 5.5 Verification Suite, design teams can dramatically speed design and verification from the initial system-level specification through to the gate-level implementation.

Features and Benefits of the QuickBench 5.5 Verification Suite
QuickBench 5.5 Verification Suite offers many enhancements including:

• Open verification architecture -- supports the use of C for speed and RAVE for granularity
• New GigaScale Hub technology -- enables design reuse and closes the gaps between all levels of abstraction -- architecture, system, RTL, and gate-level
• Expanded modeling capability -- scales to billions of gates to handle the largest designs
• Enhanced performance -- produces faster run-times and speeds-up operational productivity

Pricing and Availability
The 5.5 release of the QuickBench Verification Suite starts at U.S. $20,000 for a basic license agreement, and is available for immediate shipment. For more information on pricing, please contact Forte Sales at 800-585-4120 or visit http://www.ForteDS.com.

About Forte Design Systems, Inc.
Formed through the merger of CynApps and Chronology, Forte Design Systems provides open, integrated tools for the hierarchical design and verification of large, complex electronics systems and integrated circuits (ICs). Forte's headquarters are located at 1798 Technology Drive, in San Jose, California, 95110, U.S.A. For more information, call 800-585-4120 or visit http://www.ForteDS.com.

QuickBench 5.5 is a registered trademark and Verification Suites and GigaScale Hub are trademarks of Forte Design Systems, Inc. All other trademarks are the property of their respective owners. CynApps dba Forte Design Systems. Chronology dba Forte Design Systems.

For more information, please contact:

Brett Cline
Forte Design Systems, Inc.
978-264-1855
brett@ForteDS.com

Tim McAdams
Armstrong Kendall, Inc.
503-672-4695
tim@akipr.com